@inproceedings{pabloleyva‚2014simplification, title = {Simplification and Hardware Implementation of the Feature Descriptor Vector Calculation in the {SIFT} Algorithm}, booktitle = {24th International Conference on Field Programmable Logic and Applications}, year = {2014}, abstract = {This paper proposes a hardware implementation to speed up the calculation of the feature descriptor vector in the Scale-Invariant Feature Transform (SIFT) algorithm. The proposed architecture‚ which improves conventional solutions based on embedded processors or other hardware/software co-designs‚ computes a feature descriptor vector of 27 elements from a keypoint neighborhood of 15x15 pixels. This process comprises several steps‚ including complex operations such as vector normalization operations. The paper compares two different implementations: one being time-optimized and the other memory-optimized. Both approaches require 649 and 874 clock cycles respectively for a single feature vector calculation (6.49 μs and 8.74 μs for a 100 MHz FPGA).}, doi = {10.1109/FPL.2014.6927409}, url = {http://dx.doi.org/10.1109/FPL.2014.6927409}, author = {Pablo Leyva‚ Gines Domenech-Asensi‚ Javier Garrigos‚ Julio Illade-Quinteiro‚ Victor Brea‚ Paula Lopez and Diego Cabello} }