Development of simulation tools for advanced semiconductor devices


The work proposed will be engaged within an Spanish national project involving the multi-dimensional modelling of next-generation semiconductor nanodevices, the optimisation of numerical algorithms and the development of tools for the efficient handling of simulation data, under supervision of Natalia Seoane and Antonio García Loureiro.

The research on modelling and simulation of advanced electronic devices, using different numerical techniques implemented in one, two and three dimensions, is being held in our group ( for more than 20 years. Specifically, the study of fluctuations and material variations using drift-diffusion and Monte Carlo simulators for semiconductor devices and the implementation and optimisation of our simulators for use in new computational infrastructures is our main area of expertise.


The call seeks outstanding and highly motivated candidates, with initiative, creativity and team-working ability, including working in interdisciplinary research groups. Candidates should fulfill the following eligibility criteria:

  • Candidates must have obtained a University Degree and a Master Degree in Physics, Electronic Engineering, Telecommunication Engineering, Materials Science, Computer Sciences or in another related area within the European Higher Education System (minimum 300 ECTS) or an equivalent University Degree that allows to start a PhD Program at the University of Santiago de Compostela.
  • Excellent academic record.
  • Good computational skills.
  • Very good English level.
  • Basic knowledge on semiconductor physics, device physics and characterisation techniques.


  • Nagy D., Indalecio G., García-Loureiro A., Espiñeira G., Elmessary M., Kalna K., and Seoane N., Drift-Diffusion Versus Monte Carlo Simulated ON-Current Variability in Nanowire FETs. IEEE Access, Vol. 7, pp. 12790-12797, 2019.
  • Indalecio G., Garcia-Loureiro A.J., Seoane N. and Kalna K., Spatial Sensitivity of Silicon GAA Nanowire FETs Under Line Edge Roughness Variations. IEEE Journal of the Electron Devices Society, Vol. 6, pp. 601-610, 2018.
  • Seoane N., Indalecio G., Nagy D., Kalna K. and Garcia-Loureiro A., Impact of Cross-Sectional Shape on 10-nm Gate Length InGaAs FinFET Performance and Variability, IEEE Transactions on Electron Devices, Vol. 65, No. 2, pp. 456-462, 2018.

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