Scale- and Rotation-Invariant Feature Detectors on CMOS-3D Technology for Low-Power Vision Systems

The main goal in this project is to explore scale-, affine- and rotation-invariant feature detectors and their mapping onto CMOS-3D technologies. This project starts the way to future low-power stand-alone vision systems, which in turn could be used in: 1) embedded systems, where compact, light, low-power and high-performance platforms are needed, and/or 2) in distributed systems as wireless sensor networks, and particularly vision sensor networks, where low power consumption is a must.

Objectives

The main goal in this project is to explore scale-, affine- and rotation-invariant feature detectors and their mapping onto CMOS-3D technologies.
  1. Survey and study of SIFT and SURF algorithms
  2. Software with the incorporation of hardware errors
  3. Definition of the CMOS-3D architecture
  4. Modeling and characterization of the sensing plane
  5. Hardware implementation of the low-level tasks
  6. Hardware implementation of the high-level tasks
  7. PCB and testing of the resultant chip