Feature detection and matching on an SIMD/MIMD hybrid embedded processor

TítuloFeature detection and matching on an SIMD/MIMD hybrid embedded processor
AutoresA. Nieto, D.L. Vilariño, V.M. Brea
TipoComunicación para congreso
Fonte 2012 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops, Providence (USA), IEEE, pp. 21-26 , 2012.
ISBN978-1-4673-1612-5
ISSN2160-7508
DOI10.1109/CVPRW.2012.6238890
AbstractThis work presents the implementation of a feature detection and matching algorithm on an innovative SIMD/MIMD dynamically-reconfigurable architecture intended for high-performance embedded vision systems. An FPGA-based system-on-chip with a 128-unit coprocessor running at 150MHz is able to locate a target in 320 × 240 px images in less than 1 ms. It is also shown how to map the algorithms to speed-up the processing taking advantage of the different available computation modes.
Palabras chaveFeature detection, matching, computer vision, SIMD/MIMD reconfigurable architectures, VHDL, FPGA