Iterative Algorithm and Architecture for Exponential, Logarithm, Powering and Root Extraction

TítuloIterative Algorithm and Architecture for Exponential, Logarithm, Powering and Root Extraction
AutoresAlvaro Vázquez and Javier D. Bruguera
TipoArtículo de revista
Fonte IEEE Transactions on Computers, IEEE COMPUTER SOC , Vol. 62, No. 9, pp. 1721-1731 , 2013.
RankRanked Q1 in Hardware and Architecture by SJR
ISSN0018-9340
DOI10.1109/TC.2012.247
AbstractAn algorithm and architecture for powering computation and root extraction, with fixed-point and floating-point exponents, is presented in this paper. The algorithm is based on an optimized iterative sequence of parallel and/or overlapped operations: (1) reciprocal, (2) high-radix digit-recurrence logarithm, (3) left-to-right carry-free multiplication and (4) high-radix on-line exponential. A redundant number system is used to allow for the overlapping of the different operations of the algorithm. As the logarithm and exponential are part of the sequence of operations, some minor changes are made to allow for the independent computation of the logarithm and exponential functions. A sequential implementation of the algorithm is proposed and the execution times and hardware requirements are estimated for single and double-precision floating-point computations. These estimates are obtained for several radix, according to an approximate model for the delay and area of the main logic blocks, and help to determine the radix values which lead to the most efficient implementations.
Palabras chaveelementary functions computation, digit–recurrence algorithms, high–radix algorithms, floating–point representation, computer arithmetic