On-chip retinal image processing: performance analysis on different approaches

In this paper, the implementation of an algorithm for retinal vessel tree segmentation on three different hardware architectures is addressed. Particularly, a focal-plane processors array, a FPGA-based coarse grain parallel computer and a manycore processing system have been considered. Furthermore, three different computation paradigms have been approached,based on the features of any of the platforms: pixel-parallel single instruction and multiple data (SIMD), coarse-grain SIMD and stream processing. The algorithm consists of a set of low-level image processing steps, very common in any early vision computing. Therefore, even if this is an application oriented research, the experimental results and conclusions from the analysis are also extensive to other applications involving low- level image processing.

keywords: FPGA, SIMD, retina-vessel tree extraction