SIMD Array on FPGA for B/W Image Processing

This paper introduces a topographic implementation of an SIMD array for B/W image processing of 48×48 processing elements on an FPGA. The computation is done with Boolean and shift operators. The connectivity among processing elements is set through the classical NEWS system. The array provides the functionality of a CNNUM. The paper shows examples of algorithms and applications, and it also examines possible upscalings of the 48 × 48 array on larger FPGAs.

keywords: SIMD, topographic implementation, FPGA, CNN